The present invention general relates to a phase frequency detector (PFD) having narrow control pulses, and more specifically to a PFD by means of phase latches with a narrow control pulse, which can be used in high-speed, low-power and wide working frequency band applications, such as in a high-speed digital phase-locked loop (PLL) circuit and wide band frequency synthesizer.
Phase-locked loop is commonly used in various IC chips, such as communication IC, central processing unit (CPU) or networking IC, to achieve synchronous clock signal. In general, a phase-locked loop comprises mainly a PFD, a charge pump, a voltage controlled oscillator (VCO), and a loop filter. The PFD is used mainly to detect the difference between phase and frequency.
FIG. 1 shows a conventional tri-state PFD. Referring to FIG. 1, the PFD provides a reference signal REF as an input clock pulse, and a phase difference control signal VCO between two clock pulses in a voltage controlled oscillator. It also comprises two flip-flops 101 and 103, and an added AND gate. D terminals of both flip-flops are connected to VDD. The CLK terminal of flip-flop 101 is connected to REF. The added AND gate is an asynchronous mechanism. Flip-flops in FIG. 1 can be realized by master-slave D flip-flops, RS NAND latches or dynamic latches. FIGS. 2a-2c show three embodiments of the PFD in FIG. 1, which are master-slave D PFD, RS NAND PFD and dynamic PFD, respectively.
In FIG. 2a, the PFD uses master-slave D flip-flops of positive edge-triggered with a reset input signal Reset. Its input terminal D is connected to VDD and the CLK terminal is connected to REF.
In FIG. 2b, the PFD is realized by RS NAND latches. That is, the PFD is composed of two crossed-coupled RS NAND latches. The first latch, labeled latch_1, consists of NAND A1 and NAND B1. The second latch, labeled latch_2, consists of NAND A2 and NAND B2. latch_1 and latch_2 respond to the falling edges of the input reference signal and the reset signal, respectively. This kind of RS NAND latch using NAND gates is asynchronous and may suffer from its internal state transitions. It takes longer delay in response to the input reference signal and in generating the reset signal. Therefore, it is not suitable for high-speed and low-power PFDs.
The PFD shown in FIG. 2c is a PFD using dynamic latches that is disclosed in U.S. Pat. No. 6,157,263. It uses internal nodes to memorize the running states of the PFD. The stored charge in the internal nodes may suffer from the leakage current that is caused by unsuitable wide frequency band.
As the clock rate of the input reference signal in a PFD increases, the phase-locked loop requires higher quality. There are two major reasons causing a high-quality phase-locked loop un stable. One is that added noises may accidentally change the frequency of the voltage controlled oscillator and therefore, cause the output clock pulse of the phase-lock loop unstable. The other is that the instability is caused by a low-precision PFD. Conventional PFDs have a big minimal detectable phase difference, called dead zone, that may cause the PFD unstable. Conventional PFDs with static logic gates may cause speed limitation due to the propagation delay among the logic gates. The speed limitation broadens the dead zone under high sped running. Consequently, the instability of the PFD is increased.
The present invention has been made to overcome the above-mentioned drawback of conventional PFDs. An object of the present invention is to provide a PFD with a narrow control pulse by using a static circuit. The PFD comprises mainly two substantially equivalent phase latches of a narrow control pulse, and a reset signal generating unit.
According to the present invention, each phase latch with a narrow control pulse has a clock pulse input end and a signal output end. Both latches are also connected to the reset signal generation unit. The logic value of each signal output end is determined by which clock pulse input appears first. The reset signal generating unit decides whether or not to generate a reset signal according to the logic values of both signal output ends. The reset signal is then sent to both phase latches with a narrow control pulse if the signal is generated.
Each phase latch with a narrow control pulse comprises a narrow control pulse generating unit, a path unit, a feedback switch, a storage reset unit, and a feedback output unit. The resulting logic value of each signal output end is not affected by the use of positive or negative edge-triggered.
There are three kinds of equivalent circuitry for the preferred embodiment of the phase latch with a narrow control pulse of this invention. The design of the equivalent circuitry has two major objectives. One is to reduce the gate count used in conventional master-slave D flip-flops with reset operation. The other is to shorten the setup time of the phase latch with a narrow control pulse.
The gate count used in the phase latch with a narrow control pulse of the invention is about half of the conventional master-slave D flip-flops with reset operation. The present invention also uses a narrow control pulse and feedback control mechanism to shorten the setup time of the phase latch with a narrow control pulse. Because of the feedback control mechanism, the speed of the phase frequency detector of the invention is faster than that of a conventional dynamic PFD.
The foregoing and other objects, features, aspects and advantages of the present invention will become better understood from a careful reading of a detailed description provided herein below with appropriate reference to the accompanying drawings.